1. Field of Invention
The present invention relates to communications and more particularly to circuits and methods for providing low wander timing generation and recovery.
2. Description of Related Art
Synchronizing modulation and demodulation frequencies is made difficult by the physical separation of communication devices where each device is conceivably driven by its own local clock. Take for example, current asymmetrical digital subscriber line (ADSL) systems. Current ADSL systems operate according to Discrete Multitone (DMT) frequency multiplexing where generally the central office (CO) modem generates this master clock signal. All corresponding client modems must recover the master clock signal from downstream data for processing such as sampling, demodulation, and transmission of upstream data. While modern clocks can be manufactured with considerable accuracy, difficulties in locking remote clocks and minute differences in manufacture and calibration has to date prevented the manufacture of a high-speed modem of the highest possible performance.
Prior Art FIG. 1 is a block diagram of a communications system 10 including a transmitter 20, a receiver 22, a network 24 bi-directionally coupling the transmitter 20 and the receiver 22, and a network link clock 26. The communications system 10 illustrates one possible solution to the synchronization problem described above. In the communications system 10, both the transmitter 20 and the receiver 22 attempt to synchronize on one clock, an analog front end (AFE) or network link clock 26 having a clock signal R1. Although theoretically sound, those skilled in the art will recognize that the network link clock is simply not a viable solution for a high speed modem as jitter and wander still degrade the clock signal preventing accurate synchronization.
It is good practice to separate the network link clock that governs the transmission of data between the transmitter and the receiver from the master clock that governs the data generation source. In this way the quality of transmission within the network link 24 can be designed independently of the quality of the master clock. The difficulty inherent in this separation of clock domains is that the master clock has to be faithfully reconstructed at the receiver side to provide correctly timed, synchronous output data.
Timing recovery is therefore required at the receiver side. In timing recovery, a receiver synchronizes a local clock with a master clock present at the transmitter via phase information contained directly or indirectly in the transmitted data stream. The data modulation and demodulation process that carries the data information over the link 24 may also necessitate the two sides to use a common network link clock if the link 24 is a synchronous communication link. Receicer synchronization to the network link clock is well understood to the skilled in the art and is not going to be described here.
FIG. 2 is a block diagram of a communications system 50 implementing timing recovery of the master clock according to prior art. As will be described below, the communications system 50 recovers timing directly from the received data. The communication system 50 includes a master clock 58, a transmitter 60, a receiver 62, a network 64 bi-directionally coupling the transmitter 60 and the receiver 62, a First In First Out (FIFO) buffer 66, a control circuit 68, and a receiver clock 70. The receiver clock 70 is selected having a rate R2 known to be substantially equivalent to but slightly greater than R1, for reasons explained below.
The transmitter 60 transmits data via the network 64 at a rate R1 provided by the master clock 58 resident at the transmitter, or transported through the transmitter sourced by other network master transmitters. Data received at the receiver 62 is provided to and synchronized out through the FIFO buffer 66 at a recovered rate R1′, which is an estimate of the transmitter rate R1. The rate R1′ is obtained by the communications system 10 as follows. The FIFO buffer 66, synchronizing the data through the buffer clocked by the signal R1′, generates a signal indicative of the available buffer capacity. Available buffer capacity is indicative of the phase error between R1 and R1′ in that the FIFO buffer 66 filling up indicates that R1′ is slower than R1, and vice versa. The control circuit 68 operates on its inputs R2 and the FIFO buffer 66 error signal to generate the recovered signal R1′.
Unfortunately, the communications system 50 of FIG. 2 suffers in that a wander error will only be corrected once sufficient information is extracted from the data, which means the receiver clock can wander quite sometime before being corrected. Jitter may simply not be corrected.
What is needed is a timing generation and recovery scheme with sufficient precision to support a high-speed modem communication system.